Device modeling for MOS devices at low temperatures

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Device modeling for MOS devices at low temperatures

Briglia, F. / Fat Duen Ho

Interest in using MOS devices at temperatures in the range of 50 to 350 Cel K is increasing. In particular, MOS device operation at cryogenic temperatures is receiving considerable attention by designers of military and space-borne systems. As MOS devices are used and systems performance requirements at low temperatures increases the demand for more complete understanding of the operation or failure modes of MOS devices will increase. One- and two-dimensional models capable of providing accurate estimates of specific device parameters under specific operating conditions will contribute significantly in the development of MOS devices and understanding of their performance. Analytic models providing reasonable agreement with experiment have been developed by Jaeger and Gaensslen and Greefield and Dutton. The work of Greenfield and Dutton removed some of the limitations inherent in previous analyses due to simplifying model assumptions such as planar surfaces, planar insulator semiconductor interfaces and idealized substrate impurity distributions. In the work reported here, the one-dimensional device analysis of Jaeger and Gaensslen is extended to two dimensions using the techniques developed by Greenfield and Dutton. The two-dimensional model developed is capable of estimating the electrostatic potential and carrier concentration in an MOS transistor operating over a wide range of temperatures, but retains the simplifying assumptions of planar device structure, abrupt junctions, and idealized substrate and junction impurity distributions. The purpose of this work was to develop a two-dimensional model for solving Poisson's equation over a temperature range of 50-350 Cel K for MOS devices. This required the incorporation of temperatrue dependencies in Poisson's equation relevant to MOS transistors.