In this paper, we present an approach to model simulation systems at the Register-Transistor Level RTL for an efficient implementation on Field Programmable Gate Arrays FPGAs. The process uses a hybrid technique utilizing two commercially available tools, Simulink Coder and Xilinx Vivado HLD, as well as a middleware procedure to produce an accurate implementation of a model system in HDL, e.g. Verilog and VHDL. The implementation technique does not require expertise knowledge in Digital Design or Hardware Description Language HDL, yet it produces a complete description of the simulator in HDL. Using an example model of electric ship power system, we evaluate the effectiveness of the approach in developing a precise model in RTL for Real-Time simulation while accelerating the overall execution time.


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    Title :

    Real-Time FPGA Simulation of Electric Ship Power System Using High-Level Synthesis


    Contributors:


    Publication date :

    2019-08-01


    Size :

    1170513 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English




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