A simple high sensitivity clock recovery circuit for 40-Gbit/s return to zero signals

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A simple high sensitivity clock recovery circuit for 40-Gbit/s return to zero signals

Puleo, M. / Miras, A. / Legros, E. / Giraudet, L. / Vuye, S.

Summary form only given. Summary form only given. An all-optical optical time-division multiplexing-wavelength-division multiplexing (OTDM-WDM) interface, aimed at a capacity of 40 Gbit/s, under development in the frame of the ACTS project OPEN, realizes the conversion of an OTDM data stream into four WDM data streams, exploiting an MZI-SOA device simultaneously performing demultiplexing and wavelength conversion. The operation of this converter requires four pulsed signals at different wavelengths and at 10 GHz repetition rate, properly synchronized so that each pulse corresponds to a different bit of the incoming data stream. To achieve this synchronization, a clock recovery circuit, whose structure is reported, has been realized. The clock component at 40 GHz of the incoming RZ signal is detected by a narrow-band photoreceiver, featuring 78 dB/spl Omega/ transimpedance gain and 37 pA/spl radic/Hz noise around 40 GHz, based on a side-illuminated AlGaInAs-InP PIN diode followed by a GaAs PHEMT MMIC.