The invention provides an implementation method of a free flight model wind tunnel test system based on RS coding and decoding. The system is composed of three parts: an airborne end, a ground end and a portable upper computer. The airborne end and the ground end take an FPGA as a main control core, and the functions of the whole test system are completed by programming the FPGA. The airborne end FPGA programming logic framework is driven by double clocks, has a four-stage pipeline structure, and comprises a wireless uplink module, a wireless downlink module, an RS encoder, an RS decoder, a data packet analyzer, a data group packet, a UART (Universal Asynchronous Receiver/Transmitter) communication module, an AD (Analog/Digital) acquisition module, an information storage fifo, an information encoding fifo, an information decoding fifo and the like. Therefore, acquisition of airborne end sensor data and control of an execution mechanism are realized. And the FPGA programming logic framework at the ground end also adopts double-clock driving, is divided into a three-stage pipeline structure, and comprises a wireless uplink module, a wireless downlink module, an Ethernet module, a data packet analysis module, a data packing module and an information storage fifo. Therefore, interaction between the airborne end and the upper computer is completed. And finally, the display control system on the upper computer is used for displaying the airborne end model information. By adopting the technical scheme provided by the invention, RS coding and decoding are realized on the FPGA, and the problems that wired communication between an airborne end and a ground end is easy to interfere with a test, wireless communication is easy to be interfered by noise and the like in related system work can be solved. The system is not high in hardware complexity, guarantees the communication reliability of the test system, and is very high in applicability.

本发明提供了一种基于RS编解码的自由飞模型风洞试验系统的实现方法。该系统由三部分组成：机载端、地面端以及便携式上位机。机载端与地面端以FPGA为主控核心，通过对其编程完成整个试验系统功能。机载端FPGA编程逻辑框架采用双时钟驱动，具有四级流水线结构，包括了无线上行模块、无线下行模块、RS编码器、RS解码器、数据包解析、数据组包、UART通信模块、AD采集模块、信息存储fifo、信息编码fifo、信息译码fifo等。以此实现机载端传感器数据的采集与执行机构的控制。地面端FPGA编程逻辑框架也采用双时钟驱动，分三级流水结构，包括了无线上行模块、无线下行模块、以太网模块、数据包解析、数据组包、信息存储fifo。以此完成机载端与上位机间的交互。最终通过上位机上的显控系统完成对机载端模型信息的显示。采用本发明所述的技术方案，在FPGA上实现RS编译码，能解决相关系统工作中，机载端与地面端有线通信易干扰试验，无线通信面临易受噪声干扰等问题。该系统硬件复杂度不高，保证了试验系统通信的可靠性，具有很强的应用性。