On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers

Sie sind hier: Homepage > Suche

On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers

Freier Zugriff

García Vidal, Jorge / March Hermo, María Isabel / Cerdà Alabern, Llorenç / Corbal San Adrián, Jesús / Valero Cortés, Mateo

Abstract

We address the design of a packet buffer for future high-speed routers that support line rates as high as OC-3072 (160 Gb/s), and a high number of ports and service classes. We describe a general design for hybrid DRAM/SRAM packet buffers that exploits the bank organization of DRAM. This general scheme includes some designs previously proposed as particular cases. Based on this general scheme, we propose a new scheme that randomly chooses a DRAM memory bank for every transfer between SRAM and DRAM. The numerical results show that this scheme would require an SRAM size almost an order of magnitude lower than previously proposed schemes without the problem of memory fragmentation. ; Peer Reviewed ; Postprint (published version)

Zugriff

Download

Exportieren, teilen und zitieren

Dokumentinformationen

Titel :

On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers

Beteiligte:

García Vidal, Jorge (Autor:in) / March Hermo, María Isabel (Autor:in) / Cerdà Alabern, Llorenç (Autor:in) / Corbal San Adrián, Jesús (Autor:in) / Valero Cortés, Mateo (Autor:in) / Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors / Universitat Politècnica de Catalunya. CNDS - Xarxes de Computadors i Sistemes Distribuïts / Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions

Erscheinungsdatum :

2004-01-01

DOI :

https://doi.org/10.1109/HPSR.2004.1303414

Medientyp :

Sonstige

Format :

Elektronische Ressource

Sprache :

Englisch

Schlagwörter :

Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors , Telecommunication -- Traffic -- Management , Routing (Computer network management) , Telecommunication network routing , DRAM chips , SRAM chips , Packet switching , Buffer storage , Electronic switching systems , Queueing theory , Telecomunicació -- Tràfic -- Gestió