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Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications
Deep Space Network turbo decoder implementation
Deep Space Network turbo decoder implementation
Using 0.8 mu m DMILL technology to realize an encoder/decoder for optical transmission at 550 Mbps
Spacecraft uplink, downlink, and intercommunications in a space-qualified ASIC chip set
An analog BiCMOS integrated circuit for front-end RDS decoder
A forward error correction technique using a high-speed, high-rate single chip codec
Overview of existing and projected uses of coding in military satellite communications