Undergraduate students of the Engineering Science Department at the University of Exeter have recently begun using Electronic CAD systems as part of their coursework. This paper reports on this work. The paper outlines aspects of a railway signalling system and describes a case study using CMOS ASIC, which involved the application of fault testing. The design for testability techniques are discussed and the final test strategy and evaluation of the project is reported. Finally a summary of further developments, that could be undertaken in future project work, is provided.
The application of fault testing to a railway signalling system
Die Fehlererkennung in Eisenbahnsignalsystemen
IEE Colloquium on 'Design for Testability' ; No.32 ; 10/1-10/4
1988
, 5 Quellen
Aufsatz (Konferenz)
Englisch
ZELLULAR-ARRAY , SICHERHEIT , VLSI-SCHALTUNG , KUNDENSCHALTUNG , EISENBAHNSIGNALTECHNIK , FUNKTIONSPRUEFUNG , CMOS-SCHALTUNG , FEHLERERKENNUNG , DIGITALE INTEGRIERTE SCHALTUNG , ZUVERLAESSIGKEIT , PRUEFUNG INTEGRIERTER SCHALTUNGEN , INTEGRIERTE VERKNUEPFUNGSSCHALTUNG , LOGIKPRUEFUNG , EISENBAHN , CASE STUDY
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