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    A 300 MHz embedded flash memory with pipeline architecture and offset-free sense amplifiers for dual-core automotive microcontrollers

    A 300 MHz embedded flash memory with pipeline architecture and offset-free sense amplifiers for dual-core automotive microcontrollers


    We propose a novel 300 MHz embedded flash memory for dual-core microcontrollers targeting shared ROM architecture. One of the features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduced performance penalty due to shared ROM access conflict. The second feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch because of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and the proposed sense amplifiers achieves significant reduction in access-conflict penalties with shared ROM and enhanced performance of 32-bit RISC dual-core microcontrollers by 30%.

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    Titel :

    A 300 MHz embedded flash memory with pipeline architecture and offset-free sense amplifiers for dual-core automotive microcontrollers

    Beteiligte:
    Kajiyama, S. (Autor:in) / Fujito, M. (Autor:in) / Kasai, H. (Autor:in) / Mizuno, M. (Autor:in) / Yamaguchi, T. (Autor:in) / Shinagawa, Y. (Autor:in)
    Erschienen in:

    IEEE Asian Solid-State Circuits Conference, 2008 ; 257-260

    Erscheinungsdatum :

    2008

    Format / Umfang :

    4 Seiten, 6 Quellen

    ISBN :

    978-1-4244-2604-1

    DOI :

    https://doi.org/10.1109/ASSCC.2008.4708777

    Medientyp :

    Aufsatz (Konferenz)

    Format :

    Print

    Sprache :

    Englisch

    Schlagwörter :

    Kraftfahrzeugelektronik , Flash-Speicher , Mikrocontroller , Pipeline-System (DV) , ROM (Festwertspeicher) , RISC (Reduced Instruction Set Computer) , Kraftwagen

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