Improving the Implementation of EDAC Functions in Radiation-Hardened FPGAs

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Improving the Implementation of EDAC Functions in Radiation-Hardened FPGAs

Colodro-Conde, Carlos / Toledo-Moreo, Rafael

Error Detection and Correction (EDAC) codes have been widely used for protecting memories from single event upsets (SEU), which occur in environments with high levels of radiation or in deep submicron manufacturing technologies. This paper presents a novel synthesis algorithm that provides area-efficient implementations of EDAC functions on FPGAs, where resource utilization usually needs to be kept to a minimum in order to embrace more logic in a single die. The algorithm under consideration has been tested selecting two models of radiation-hardened FPGAs: one from the RT ProASIC3 series (flash-based) and another one from the RTAX-S series (antifuse-based). The results show that, when compared to the commercial synthesis tool provided by the vendor of the selected FPGA models, the proposed algorithm reduces number of used combinational cells up to a 23.5 %, while providing generally better timing performances (up to 23.6 % faster maximum path delays for the post-place and route implementations).