Implementation of a Multi-Core Data Link Layer Processor for THz Communication

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Implementation of a Multi-Core Data Link Layer Processor for THz Communication

Lopacinski, L. / Eissa, M. H. / Panic, G. / Brzozowski, M. / Hasani, A. / Kraemer, R.

In this paper, we discuss the main challenges and our solutions proposed for implementation of a high-speed data link layer processor. Our target is to achieve processing throughput faster than 20 Gbps. Meanwhile a single core of our implementation achieves ''only'' ~28 Gbps, we propose a multi-core solution that can run up to ~110 Gbps. For this purpose, we use baseband signal splitters and combiners. Alternatively, we come up with Parallel Sequence Spread Spectrum (PSSS). After splitting the input signal, we divide the required processing-effort among a set of parallel baseband and data link layer processors. The discussed data link layer processor uses hybrid-automatic-repeat-request-I (HARQ-I) with link adaptation and selective fragment repetitions. Such solution significantly improves the efficiency of the method and allows to reduce the implementation complexity when compared to HARQ-III. The main issue discussed in the article is power and energy consumption. Our solution consumes maximally 300 mW at 27.9 Gbps, including forward error correction (FEC) engine.

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Dokumentinformationen

Titel :

Implementation of a Multi-Core Data Link Layer Processor for THz Communication

Beteiligte:

Lopacinski, L. (Autor:in) / Eissa, M. H. (Autor:in) / Panic, G. (Autor:in) / Brzozowski, M. (Autor:in) / Hasani, A. (Autor:in) / Kraemer, R. (Autor:in)

Erschienen in:

2018 IEEE 87th Vehicular Technology Conference (VTC Spring) ; 1-5

Erscheinungsdatum :

2018-06-01

Format / Umfang :

361414 byte

ISBN :

978-1-5386-6355-4 , 978-1-5386-6354-7

ISSN :

2577-2465

DOI :

https://doi.org/10.1109/VTCSpring.2018.8417522